The present invention generally relates to arithmetic digital circuits and more specifically relates to error detection circuits.
The introduction and widespread use of large scale integrated circuit (LSI) technologies have made possible the incorporation of complex functions within a single device. As a result, many contemporary systems have performance and price characteristics which have significant advantages over previous systems but which introduce some new problems. Of most interest to the present invention is the use of LSI devices to perform complex arithmetic tasks. Because the arithmetic relationship between the inputs and outputs may be quite complex, scaling of the resultant, especially for fixed-point operations, can become difficult. Normally, the scale factor to be used in scaling the output (i.e., postscaling) is determined in advance of the actual arithmetic operation. Whereas this causes efficiency in post scaling, it does tend to cause overflow conditions.
It is very difficult and time consuming to determine the presence of an overflow condition from the data following the postscaling operation, though this approach is common in the art. It would be more desirable to check for an overflow condition before postscaling, but the problem is greatly complicated if the scale factor to be used in postscaling is a variable.